• DocumentCode
    995653
  • Title

    Digital measurement of polysilicon to diffusion misalignment for a silicon gate MOS process

  • Author

    Walton, A.J. ; Gammie, W.R. ; Holwill, R. ; Henderson, B.M.M.

  • Author_Institution
    University of Edinburgh, Edinburgh Microfabrication Facility Department of Electrical Engineering, Edinburgh, UK
  • Volume
    20
  • Issue
    23
  • fYear
    1984
  • Firstpage
    951
  • Lastpage
    952
  • Abstract
    A MOS structure which digitally measures the misalignment between polysilicon and diffusion which occurs during processing is presented. The ultimate resolution of the structure is dependent only on the process resolution, with the measurement being based on conduction due to misaligned polysilicon gates. The design automatically compensates for any overetching which may have occured during processing.
  • Keywords
    integrated circuit technology; metal-insulator-semiconductor structures; semiconductor device testing; IC technology; MOS structure; Si gate MOS process; digital measurement; misalignment measurement; overetching compensation; parametric testing; polysilicon to diffusion misalignment; process resolution;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19840647
  • Filename
    4249160
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=995653