Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

Author

Amusan, Oluwole A. ; Massengill, Lloyd W. ; Bhuva, Bharat L. ; DasGupta, Sandeepan ; Witulski, Arthur F. ; Ahlbin, Jonathan R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN

Volume

54

Issue

6

fYear

2007

Firstpage

2060

Lastpage

2064

Abstract

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.

Keywords

CMOS logic circuits; MOSFET; combinational circuits; radiation hardening; radiation hardening (electronics); CMOS SET response; PMOS device; SET pulse width reduction; charge collection; charge redistribution; deep submicron combinational logic; matched-current-drive inverter chain; n-well contact layout; parasitic bipolar amplification; radiation hardened by design; single event transient pulse; transistor sizing; Bipolar transistors; CMOS logic circuits; CMOS technology; Design optimization; Logic design; Logic devices; MOS devices; Pulse measurements; Radiation hardening; Space vector pulse width modulation; Charge collection; charge confinement; lateral parasitic bipolar; n-well collapse; n-well contact area; n-well contact location; radiation hardened by design; transistor sizing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2007.907754

Filename

4394993