• DocumentCode
    995842
  • Title

    Disintermediated Active Communication

  • Author

    Bracy, Anne ; Doshi, Kshitij ; Jacobson, Quinn

  • Volume
    5
  • Issue
    2
  • fYear
    2006
  • Firstpage
    15
  • Lastpage
    15
  • Abstract
    Disintermediated active communication (DAC) is a new paradigm of communication in which a sending thread actively engages a receiving thread when sending it a message via shared memory. DAC is different than existing approaches that use passive communication through shared-memory - based on intermittently checking for messages - or that use preemptive communication but must rely on intermediaries such as the operating system or dedicated interrupt channels. An implementation of DAC builds on existing cache coherency support and exploits light-weight user-level interrupts. Inter-thread communication occurs via monitored memory locations where the receiver thread responds to invalidations of monitored addresses with a light-weight user-level software-defined handler. Address monitoring is supported by cache line user-bits, or CLUbits. CLUbits reside in the cache next to the coherence state, are private per thread, and maintain user-defined per-cache-line state. A light weight software library can demultiplex asynchronous notifications and handle exceptional cases. In DAC-based programs threads coordinate with one another by explicit signaling and implicit resource monitoring. With the simple and direct communication primitives of DAC, multi-threaded workloads synchronize at a finer granularity and more efficiently utilize the hardware of upcoming multi-core designs. This paper introduces DAC, presents several signaling models for DAC-based programs, and describes a simple memory-based framework that supports DAC by leveraging existing cache-coherency models. Our framework is general enough to support uses beyond DAC
  • Keywords
    cache storage; interrupts; multi-threading; shared memory systems; software libraries; storage allocation; CLUbits; address monitoring; cache coherency; cache line user-bits; disintermediated active communication; interthread communication; memory locations; multicore designs; resource monitoring; shared memory; signaling models; software library; user-level interrupts; Computer aided instruction; Concurrent computing; Hardware; High performance computing; Monitoring; Operating systems; Processor scheduling; Programming profession; Software libraries; Yarn;
  • fLanguage
    English
  • Journal_Title
    Computer Architecture Letters
  • Publisher
    ieee
  • ISSN
    1556-6056
  • Type

    jour

  • DOI
    10.1109/L-CA.2006.15
  • Filename
    4069172