A single chip MPEG1 decoder

Author

Kawahara, K. ; Yamauchi, H. ; Okada, S.

Author_Institution

Microelectron. Res. Center, Sanyo Electr. Co. Ltd., Gifu, Japan

Volume

41

Issue

3

fYear

1995

fDate

8/1/1995 12:00:00 AM

Firstpage

707

Lastpage

715

Abstract

A single chip MPEG1 decoder was developed. It contains a video decoder, an audio decoder and a system decoder for MPEG1 and also include a CD-ROM decoder for a package media application. The outstanding feature of the chip is its high quality control of MPEG1 system such as buffer management and AV synchronization. The chip basically decodes a MPEG1 stream automatically with minimal support from an external microprocessor. The circuits were designed using a dedicated hardwired logic resulting in a low cost and low power chip. The chip was fabricated in triple metal 0.5 micron CMOS technology. It dissipates about 400 mW power with 54 MHz clock and 3.3 V voltage supply

Keywords

CD-ROMs; CMOS digital integrated circuits; code standards; decoding; digital signal processing chips; large scale integration; telecommunication standards; video equipment; 0.5 micron; 3.3 V; 400 mW; 54 MHz; AV synchronization; CD-ROM decoder; LSI; audio decoder; buffer management; clock; dedicated hardwired logic; low cost chip; low power chip; package media application; power; single chip MPEG1 decoder; system decoder; triple metal 0.5 micron CMOS technology; video decoder; voltage supply; CD-ROMs; CMOS technology; Decoding; Microprocessors; Packaging; Power system management; Quality control; Quality management; Streaming media; Synchronization;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.468019

Filename

468019