DocumentCode :
996074
Title :
Optimizing Radiation Hard by Design SRAM Cells
Author :
Clark, Lawrence T. ; Mohr, Karl C. ; Holbert, Keith E. ; Yao, Xiaoyin ; Knudsen, Jonathan ; Shah, Harshit
Author_Institution :
Arizona State Univ., Tempe
Volume :
54
Issue :
6
fYear :
2007
Firstpage :
2028
Lastpage :
2036
Abstract :
Various radiation hardened by design SRAM cells are explored for their size, electrical performance, and total ionizing dose (TID) immunity. TID experiments using Co-60 testing on 130- and 90-nm transistors and SRAM arrays show that SRAM cells using two-edge transistors, NMOS access transistors, and NMOS reverse-body-bias effectively mitigate TID in both generations. This work experimentally demonstrates that commercial foundry (optimally sized) SRAM cells can be used in radiation hardening by design if NMOS reverse-body bias is used for TID mitigation.
Keywords :
MOSFET; SRAM chips; radiation hardening (electronics); NMOS access transistors; NMOS reverse-body-bias; SRAM cells; radiation hardening by design optimization; size 130 nm; size 90 nm; total ionizing dose; two-edge transistors; Design optimization; Foundries; Ionizing radiation; Latches; MOS devices; MOSFETs; Radiation hardening; Random access memory; Sequential circuits; Single event upset; Integrated circuit radiation effects; SRAM; radiation hardening;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2007.909482
Filename :
4395012
Link To Document :
بازگشت