An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs

The input referred offset voltage occurring in the full latch V/sub DD/ biased sense amplifier has been analyzed extensively. The process variations in the matched nMOS and pMOS transistors have been accounted by /spl plusmn/2.5% variation in V/sub T/ and /spl plusmn/5% variation in /spl beta/, from typical values. Effect of various design parameters on the sense amplifier offset has been studied and reported. It has been shown that the rise time of the sense amplifier enable signal (SAEN) has a profound effect on the offset voltage. The slower transition of SAEN signal is proposed to result in high speed as well as low-power consumption in SRAM application. An analytical model has been derived for simplified latch to model the effect of rise time of SAEN signal on offset voltage.