Title :
Linear equivalence of certain BRM shift-register sequences
Author :
Chambers, W.G. ; Jennings, S.M.
Author_Institution :
Westfield College, University of London, Mathematics Department, London, UK
Abstract :
A theorem given by Albert is used to show that if a shift register of length m is used to clock another shift register of length n through a binary rate-multiplier, then it can easily be arranged that the output has a linear equivalence of (2m ¿ 1)n and a period of (2m ¿ 1)(2n ¿ 1).
Keywords :
binary sequences; shift registers; binary rate-multiplier; binary sequences; linear equivalence; shift-register sequences;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19840693
