DocumentCode
996203
Title
Scaling theory for fault stealing algorithms in large systolic arrays
Author
Stornetta, W. Scott ; Huberman, Bernardo A. ; Hogg, Tad
Author_Institution
Dept. of Phys., Stanford Univ., CA, USA
Volume
9
Issue
3
fYear
1990
fDate
3/1/1990 12:00:00 AM
Firstpage
290
Lastpage
298
Abstract
The performance of fault-stealing algorithms for very large, multipipeline systolic arrays is considered. Extensions of an existing algorithm are proposed, and with these extensions the algorithm is shown to work for large array sizes. Using the modified algorithms as a testbed, a scaling theory that predicts, on the basis of performance for a single small array, the performance of the algorithm for arbitrary array size, defect rate, and number of spares is introduced. The theory differs from current approaches in that it has both analytical and empirical components, and in that it accurately predicts system performance, rather than providing bounds on it
Keywords
VLSI; algorithm theory; cellular arrays; circuit reliability; parallel algorithms; parallel architectures; pipeline processing; redundancy; VLSI; WSI; defect rate; fault stealing algorithms; fault tolerance; large systolic arrays; manufacturing defects; multipipeline; reliability; scaling theory; spares utilisation; system performance prediction; Computational modeling; Computer networks; Concurrent computing; Nearest neighbor searches; Performance analysis; System performance; Systolic arrays; Testing; Very large scale integration; Wafer scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.46804
Filename
46804
Link To Document