DocumentCode
996315
Title
On computing the sizes of detected delay faults
Author
Iyengar, Vijay S. ; Rosen, Barry K. ; Waicukauski, John A.
Author_Institution
IBM Res. Div., Yorktown Heights, NY, USA
Volume
9
Issue
3
fYear
1990
fDate
3/1/1990 12:00:00 AM
Firstpage
299
Lastpage
312
Abstract
Defects in integrated circuits can cause delay faults of various sizes. Testing for delay faults has the goal of detecting a large fraction of these faults for a wide range of fault sizes. Hence, an evaluation scheme for a delay fault test must not only compute whether or not a delay fault was detected, but also calculate the sizes of detected delay faults. Delay faults have the counterintuitive property that a test for a fault of one size need not be a test for a similar fault of a larger size. This makes it difficult to answer questions about the sizes of delay faults detected by a set of tests. A model for delay faults that answers such questions correctly, but with calculations simple enough to be done for large circuits, is presented
Keywords
delays; fault location; integrated circuit testing; integrated logic circuits; logic testing; delay fault test; detected delay faults; detection thresholds; fault model; fault sizes; integrated circuits; logic testing; scan designs; Circuit faults; Circuit testing; Delay; Design optimization; Electrical fault detection; Fault detection; Graphics; Logic; Signal analysis; Timing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.46805
Filename
46805
Link To Document