Title :
An experimental large-capacity semiconductor file memory using 16-levels/cell storage
Author :
Horiguchi, Masahi ; Aoki, Masakazu ; Nakagome, Yoshinobu ; Ikenaga, Shin´Ichi ; Shimohigashi, Katsuhiro
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A 4-bit semiconductor file memory using 16-levels (4-bits)/cell storage is described. The device has 1-Mb single-transistor dynamic memory cells which are divided into 4-kb sequential-access blocks. It incorporates a staircase-pulse generator for multilevel storage operations, a voltage regulator to protect against power-supply voltage surge, and a soft-error-correction circuit based on a cyclic hexadecimal code. The device is fabricated using 1.3- mu m CMOS technology. It operates with a 5-V single power supply. Random block selection time is 147 mu s, while the sequential data rate is 210 ns. A single-incident alpha particle destroys 4-bit data in two or more adjacent cells. The error correction circuit completely corrects these errors. The soft-error rate under actual operating conditions with error correction is expected to be under 100 FIT (10/sup -7/ h/sup -1/).<>
Keywords :
CMOS integrated circuits; error correction; integrated memory circuits; surge protection; 1.3 micron; 147 mus; 16-levels/cell storage; 210 ns; 4 Mbit; 5 V; 5-V single power supply; CMOS technology; cyclic hexadecimal code; large-capacity; multilevel storage operations; semiconductor file memory; sequential data rate; sequential-access blocks; single-transistor dynamic memory cells; soft-error-correction circuit; staircase-pulse generator; voltage regulator; voltage surge protection; Circuits; Computer errors; Error correction; Power generation; Power supplies; Protection; Pulse generation; Regulators; Threshold voltage; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
