DocumentCode :
996523
Title :
Area optimization of delay-optimized structures using intrinsic constraint graphs
Author :
Peyran, Olivier ; Zeng, Zheng ; Zhuang, Wenjun
Author_Institution :
Inst. of High Performance Comput., Singapore
Volume :
23
Issue :
6
fYear :
2004
fDate :
6/1/2004 12:00:00 AM
Firstpage :
888
Lastpage :
906
Abstract :
In this paper, we present a new methodology for structure optimization of block-based design. Instead of merging area and delay criteria, we segregate them into two independent steps. Solutions optimized for delay in the first step are optimized for area with a block-sizing algorithm in the second step. The fully optimized solutions eventually return to the first optimization step, if the user constraints are not met, using a structure-extraction module. A condition to this approach is that the area optimization phase does not alter the quality reached during delay optimization. We propose a framework for area optimization of delay-optimized structures based on structure similarities. We present a new model to represent block placements that share the same qualities for global routing. Using this model, we formally define the relation of similarity and exhibit several properties and theorems to validate our approach. The modules composing the area optimization phase are presented and experimental results confirm the validity of our methodology.
Keywords :
circuit layout CAD; circuit optimisation; constraint theory; data flow graphs; integrated circuit interconnections; integrated circuit layout; network routing; signal flow graphs; area optimization; block placements; block-based design; block-sizing algorithm; chip planning optimization; delay optimization; delay-optimized structures; global routing; graph modeling; intrinsic constraint graphs; slicing structures; structure optimization; structure-extraction module; user constraints; Associate members; Computer science; Constraint optimization; Delay; Design optimization; Integrated circuit interconnections; Merging; Routing; Shape; Timing; Block sizing; chip planning optimization; graph modeling; slicing structures;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2004.828124
Filename :
1302189
Link To Document :
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