A Novel Circuit-Level SEU Hardening Technique for High-Speed SiGe HBT Logic Circuits

In this work we present a new circuit-level hardening technique for SEU mitigation in high-speed SiGe BiCMOS digital logic. A reduction in SEU vulnerability is realized through the implementation of an additional storage cell redundancy block to achieve the required decoupling. When compared with latch duplication, current sharing or gated feedback techniques, this method incurs a lower power penalty and no speed penalty. The hardened circuit is implemented in CML and LVL families and circuit simulation models predict significant reduction in the number of upsets compared to the corresponding unhardened versions. The technique is also easy to incorporate into existing designs.