Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive

Author

Ionescu, A.M. ; Mahapatra, S. ; Pott, V.

Author_Institution

Electron. Lab., Swiss Fed. Inst. of Technol., Lausanne, Switzerland

Volume

25

Issue

6

fYear

2004

fDate

6/1/2004 12:00:00 AM

Firstpage

411

Lastpage

413

Abstract

A hybrid single electron transistor/MOSFET (SETMOS) circuit cell architecture, working as a three-terminal stand-alone device for obtaining SET-like Coulomb blockade oscillations, along with a high current drive ( /spl sim/ μA), is proposed. SETMOS characteristics are successfully predicted by analytical models at subambient (-100 /spl deg/C to -150 /spl deg/C) temperature with realistic device parameters. The effect of bias voltages and current on the SETMOS Coulomb blockade oscillations characteristics is critically discussed. It is also demonstrated that the SETMOS can be converted into a unique quasi-periodic negative differential resistance (NDR) device by short-circuiting its gate and drain terminals.

Keywords

Coulomb blockade; MOSFET; circuit simulation; negative resistance devices; semiconductor device models; single electron transistors; -100 to -150 C; Coulomb Blockade oscillations; MOSFET circuit cell architecture; bias current; bias voltages; circuit simulation; high current drive; hybrid SETMOS architecture; quasiperiodic negative differential resistance; semiconductor device model; single electron transistor; three-terminal stand-alone device; Analytical models; CMOS technology; Capacitance; MOSFET circuits; Nanoscale devices; Power MOSFET; Semiconductor device modeling; Single electron transistors; Temperature; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2004.828558

Filename

1302243