A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

Author

Yoo, Changsik ; Kyung, Kye-Hyun ; Lim, Kyunam ; Lee, Hi-Choon ; Chai, Joon-Wan ; Heo, Nak-Won ; Lee, Dong-Jin ; Kim, Chang-Hyun

Author_Institution

Div. of Electr. & Comput. Eng., Hanyang Univ., Seoul, South Korea

Volume

39

Issue

6

fYear

2004

fDate

6/1/2004 12:00:00 AM

Firstpage

941

Lastpage

951

Abstract

A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-μm DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation.

Keywords

DRAM chips; SRAM chips; calibration; integrated circuit design; low-power electronics; 0.12 mum; 1.8 V; 512 Mbyte; CMOS; DDR-II SDRAM; DRAM process; data access time; double data rate; fully shielded data lines; hierarchical I/O lines; high data rate; local sense amplifier; low supply voltage; off-chip driver calibration; on-die termination; signal integrity; Bandwidth; Calibration; DRAM chips; Driver circuits; Energy consumption; Low voltage; Multimedia systems; Random access memory; Resistors; SDRAM; CMOS; DDR; DDR-II; DRAM; SDRAM; double data rate; hierarchical I/O line; local sense amplifier; low voltage; off-chip driver; on-die termination;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.827806

Filename

1302271