DocumentCode :
997796
Title :
Implementing a Built-In Self-Test PLA Design
Author :
Treuer, Robert ; Fujiwara, Hideo ; Agarwal, Vinod K.
Author_Institution :
McGill University
Volume :
2
Issue :
2
fYear :
1985
fDate :
4/1/1985 12:00:00 AM
Firstpage :
37
Lastpage :
48
Abstract :
An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existing scheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independent of the functions that the PLA realizes, and the 15-percent overhead includes the storage needed for the fault-free compressed output data. The fault coverage of this approach consists of all single and (1-2 -( 2n + m)) of all multiple stuck, crosspoint, and bridging faults in the original PLA and the additional test circuitry (n and m are the number of input variables and product terms, respectively). The article begins with a short review of existing design schemes.
Keywords :
Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Delay; Fault detection; Logic design; Programmable logic arrays; Routing; Test pattern generators;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.1985.294859
Filename :
4069541
Link To Document :
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