Ion implantation of neon in silicon for planar amorphous isolation

A new planar isolation technique for silicon integrated circuits is presented. The process uses neon implantation to create high-resistivity regions of amorphous silicon between active devices on a common substrate. Excellent surface planarity is obtained, and no high-temperature processing ii required. Results on test devices and an amorphous isolated m.n.o.s. capacitor memory are described.