• DocumentCode
    998930
  • Title

    Research in Design Automation for VLSI Layout

  • Author

    Kozawa, Tokinori ; Terai, Hidekazu

  • Author_Institution
    Hitachi Central Research Laboratory
  • Volume
    2
  • Issue
    5
  • fYear
    1985
  • Firstpage
    43
  • Lastpage
    53
  • Abstract
    Since Japanese R&D efforts began in the late 1960s, advances in LSI circuit design automation have made possible the design of custom logic VLSI circuits with up to 10,000 gates. Automatic placement and routing programs have become essential DA tools in both master-slice LSI circuit design, and the custom design of VLSI circuits with up to 100,000 gates. Algorithms for VLSI DA systems include automatic floor planning, automatic cell placement, and automatic routing. Hierarchical design is an efficient approach to the layour of huge numbers of transistors; a VLSI circuit with 74,000 transistors and 17,000 gates was designed using such an approach. The layout design effort required less than 10 man-months, and the chip was fabricated with no error on the first design.
  • Keywords
    Automatic logic units; Design automation; Floors; Large scale integration; Logic circuits; Logic design; Research and development; Routing; Very large scale integration; Wiring;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.1985.294816
  • Filename
    4069660