استاتيك CMOS توليد سلول استاندارد بهينه در تكنولوژي

Optimized Standard Cell Generation for Static CMOS Technology

Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Eulerian path should be found for the logic function. Every discontinuity causes an increase in the area as well as a reduction in the dock rate and performance. The realization of a logic function using the static CMOS technology is done through different methods, most of which are based on the Ueharaʹs method In this paper, an algorithm is suggested that finds the Eulerian path and allows the implementation of the circuit with continuity in the diffusion region that results in minimum area. In a case where there is no Eulerlan path, the possible sub-paths are found In addition, the algorithm gives information that helps the layout generation.