ﻃﺮاﺣﯽ و ﭘﯿﺎدهﺳﺎزي ﺷﻤﺎرﻧﺪة ﻓﺮﮐﺎﻧﺲﺑﺎﻻي ﻫﻮﺷﻤﻨﺪ ﺑﺎ ﻣﻌﻤﺎري ﺑﻬﯿﻨﻪﺷﺪه ﺑﺮ روي ﺗﺮاﺷﮥ FPGA ارزانﻗﯿﻤﺖ XC6SLX9-2FTG256C

Design and Implementation of an Intelligent High Frequency Counter with Optimized Architecture on a Low Cost FPGA Chip XC6SLX9-2FTG256C

ﺑﺮاي ﭘﯿﺎدهﺳﺎزي ﺷﻤﺎرﻧﺪهﻫﺎي ﻓﺮﮐﺎﻧﺲ ﺑﺎﻻ از روشﻫﺎي ﻣﺒﺘﻨﯽ ﺑﺮ ﺗﺮاﺷﻪﻫﺎي ﻣﺪار ﻣﺠﺘﻤﻊ وﯾﮋه ﺑﺮﻧﺎﻣﻪ )ASIC( و ﯾﺎ ﻣﺒﺘﻨﯽ ﺑﺮ ﭘﺮدازﻧﺪهﻫﺎ اﺳﺘﻔﺎده ﻣﯽﺷﻮد. ﻫﺮ ﮐﺪام از اﯾﻦ روشﻫﺎ در ﻗﺎﻟﺐ ﯾﮏ ﻣﻌﻤﺎري ﻣﺘﻔﺎوت ﭘﯿﺎدهﺳﺎزي ﻣﯽﺷﻮﻧﺪ. ﺑﺎ ﺗﻮﺟﻪ ﺑﻪ ﻣﺰاﯾﺎ و ﻣﻌﺎﯾﺐ ﻫﺮ ﮐﺪام از اﯾﻦ روشﻫﺎ و ﻣﻌﻤﺎريﻫﺎ و ﻫﻤﭽﻨﯿﻦ ﻧﻮع ﮐﺎرﺑﺮد ﺷﻤﺎرﻧﺪه، روش و ﻣﻌﻤﺎري ﻣﻨﺎﺳﺐ اﻧﺘﺨﺎب ﻣﯽﺷﻮد. در اﯾﻦ ﻣﻘﺎﻟﻪ، ﺑﺎ اﺳﺘﻔﺎده از ﻣﻌﻤﺎري ﭘﺎﻟﺲﻫﺎي ﺳﺎﻋﺖ داراي اﺧﺘﻼف ﻓﺎز، ﺷﻤﺎرﻧﺪهاي ﺑﺎ ﻓﺮﮐﺎﻧﺲ 2 ﮔﯿﮕﺎﻫﺮﺗﺰ )ﺗﻔﮑﯿﮏﭘﺬﯾﺮي زﻣﺎﻧﯽ 500 ﭘﯿﮑﻮﺛﺎﻧﯿﻪ( ﺑﺮ روي ﺗﺮاﺷﮥ آراﯾﻪ-درﯾﭽﻪ ﺑﺮﻧﺎﻣﻪﭘﺬﯾﺮ ﻣﯿﺪاﻧﯽ )FPGA( ارزانﻗﯿﻤﺖ XC6SLX9-2FTG256C از ﺧﺎﻧﻮادة اﺳﭙﺎرﺗﺎن 6 )Spartan6( ﭘﯿﺎدهﺳﺎزي ﺷﺪه اﺳﺖ. از آﻧﺠﺎ ﮐﻪ ﻣﻨﺎﺑﻊ ﺳﺨﺖاﻓﺰاري ﻣﻮﺟﻮد در ﺗﺮاﺷﮥ ﯾﺎد ﺷﺪه ﺑﺮاي ﭘﯿﺎدهﺳﺎزي اﯾﻦ ﻃﺮح ﮐﺎﻓﯽ ﻧﯿﺴﺖ و ﻫﻤﭽﻨﯿﻦ ﺗﺄﺧﯿﺮﻫﺎي ذاﺗﯽ ﻣﻨﺎﺑﻊ ﺳﺨﺖاﻓﺰاري داﺧﻞ ﺗﺮاﺷﻪ در ﺣﺪ ﭼﻨﺪ ﻧﺎﻧﻮﺛﺎﻧﯿﻪ اﺳﺖ. دﺳﺖﯾﺎﺑﯽ ﺑﻪ دﻗﺖ ﯾﺎد ﺷﺪه اﻫﻤﯿﺖ زﯾﺎدي دارد و ﻣﻌﻤﺎري اﺳﺘﻔﺎده ﺷﺪه ﻧﯿﺰ ﺑﺎﯾﺪ ﺑﻬﯿﻨﻪﺳﺎزي ﺷﻮد. ﺑﺮاي دﺳﺖﯾﺎﺑﯽ ﺑﻪ دﻗﺖ ﯾﺎد ﺷﺪه، ﻻزم اﺳﺖ ﺷﻤﺎرﻧﺪهﻫﺎﯾﯽ ﺑﺎ ﻓﺮﮐﺎﻧﺲ ﭘﺎﻟﺲ ﺳﺎﻋﺖ ﺑﺎﻻ، ﻟﺮزش و ﮐﺠﯽ ﮐﻢ و ﺑﺪون واﺑﺴﺘﮕﯽ ﺑﻪ زﻣﺎنﻫﺎي ﻧﮕﻪداﺷﺖ و ﺗﻨﻈﯿﻢ، ﻃﺮاﺣﯽ و ﭘﯿﺎده-ﺳﺎزي ﺷﻮﻧﺪ. ﻫﻤﭽﻨﯿﻦ ﺑﺮاي ﺟﺒﺮان ﮐﻤﺒﻮد ﻣﻨﺎﺑﻊ ﺳﺨﺖاﻓﺰاري ﻣﻮرد ﻧﯿﺎز ﺟﻬﺖ ﭘﯿﺎدهﺳﺎزي ﻣﺴﯿﺮﺑﻨﺪي ﭘﺎﻟﺲ ﺳﺎﻋﺖ، از ﻣﻨﺎﺑﻊ ﺳﺨﺖاﻓﺰاري ﺟﺎﯾﮕﺰﯾﻦ اﺳﺘﻔﺎده ﺷﺪه اﺳﺖ.

In this paper, a 2 GHz counter is implemented on a low-cost XC6SLX9-2FTG256C field-programmable gate array (FPGA) chip from the Spartan6 family with a 500 ps resolution. Since the hardware resources contained in this chip are not sufficient to implement this design, and also the inherent delays of the hardware resources inside the chip are about few nanoseconds, achieving this accuracy is very important. The architecture used in this research is based on the phase difference clocks that has been implemented after optimization. To achieve this accuracy, it is necessary to design and implement counters with high clock frequency, low jitter and low skew, without dependence on hold time and setup time. Alternative hardware resources have also been used to compensate for the lack of hardware resources required to implement routing clocks.