روشي براي بازيافت پالس ساعت در مودم پايانه ماهواره اي SCPC

A Method for Clock Recovery in SCPC MODEMS

Synchronization in communication systems is of great importance. Synchronization techniques are used for carrier, clock and framming recovery. In clock synchronization, the decision device in receiver recovers the correct sampling time of the received baseband signal and along with the information bearing data passes it to the next stage for decoding and descrambling. Clock synchronization techniques vary widely in both analog and digital schemes. In this paper, the use of the Digital Phase Lock Loop (DPLL) circuit along in a scheme proposed by M.F.Gardner for estimating the sampling time error appearing in the clock recovery process is first discussed. Then, a method for clock recovery in the demodulator section of an SCPC earth station terminal is proposed. Also the hardware implementation technique using the digital signal processor TMSJ20 C25, is described.