Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modifications to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and performance overheads. The proposed technique allows us to achieve complete coverage of detectable delay faults by allowing any two-pattern test to be applied to the circuit through its functional path. In addition to the basic approach, we study the proposed procedure in the presence of a constraint that requires that extra logic would not be placed on the critical paths of the circuit.