Slow-trap profiling of NO and N2O nitrided oxides grown on Si and SiC substrates

New layout design to effectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered during the ESD-stress events. With theoretical calculation and experimental verification, both higher output driving/ sinking current and stronger ESD robustness of CMOS output buffers can be practically achieved by the proposed new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional finger-type layout. © 1999 Elsevier Science Ltd. All rights reserved.