Wafer mapping of ESD performance

This paper reports, for the first time, on a variation of the ESD performance of CMOS ICs across the wafer. A variation of the TLM-ESD failure threshold by as much as a factor of 4 (four) was found within a single wafer. Comparable results were found for HBM-ESD tests. Implications of this finding for process control and ESD qualification are discussed. As main conclusion, ESD wafer mapping for process and 10 library qualification is proposed. © 1999 Elsevier Science Ltd. All rights reserved.