Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System

Modulo 2n+1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2n+1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 21+1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and delay.