Customizing the branch predictor to reduce complexity and energy consumption

To exploit instruction-level parallelism, high-end processors use branch predictors consisting of many large, often underutilized structures that cause unnecessary energy waste and high power consumption. By adapting the branch target bufferʹs size and dynamically disabling a hybrid predictorʹs components, the authors create a customized branch predictor that saves a significant amount of energy with little performance degradation.