Reducing power dissipation, delay, and area in logic circuits by narrowing transistors

An important aspect of fast CMOS logic-circuit design is transistor sizing. Designers routinely set transistor channel lengths at the minimal values the process permits (unless there is a need to introduce delay). Specification of channel widths, however, requires careful consideration and is based mainly on the capacitive load the circuit must drive and on considerations of energy dissipation and chip area. Experienced designers use heuristic techniques to help with this aspect of circuit design. Sutherland and his associates have developed a powerful systematic method called logical effort. We present a method, based on an analysis at the logic level, enables designers to identify transistors in certain logic elements whose channels can be narrowed to a minimum without incurring penalties. The logical effort method, or some other procedure, can then follow this preliminary step.