Improving the accuracy and efficiency of junction capacitance characterization: strategies for probing configuration and data set size

In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy.