Performance projections of scaled CMOS devices and circuits with strained Si-on-SiGe channels

Device and circuit simulations using a process/physics-based compact MOSFET model (UFPDB) are done to project the scaled CMOS speed-performance enhancement that can be expected from strained-Si channels on relaxed Si/sub 1-x/Ge/sub x/ buffer layers in bulk Si. With the UFPDB process-based parameters associated with carrier mobility and velocity defined physically in terms of the Ge content x (0