DocumentCode
11065
Title
Design Verification for Sequential Systems at Various Abstraction Levels
Author
G. Q. Lu استاد مشاور , Joseph G. Tront استاد مشاور , Michael S. Hsiao استاد راهنما
University
Virginia Polytechnic Institute and state University
Grade
نامعلوم
Major
PhD )Electrical and Computer Engineering(
Number of pages
0
Publish Date
2005
Keyword
Bounded Model Checking , Formal verification , SIMULATION , Sat , ATPG
Note
01
Language
انگليسي
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