مرکز منطقه ای اطلاع رساني علوم و فناوري - Hardware Accelerator for Duo-binary CTC decoding: Algorithm Selection, HW/SW Partitioning and FPGA Implementation

DocumentCode :

27398

Title :

Hardware Accelerator for Duo-binary CTC decoding: Algorithm Selection, HW/SW Partitioning and FPGA Implementation

University :

Diva Partal academic Arshive Online

Grade :

نامعلوم

Major :

Undergraduate thesis

Number of pages :

Publish Date :

2006

Keyword :

Error Correcting Codes , decoding , FPGA , Turbo codes , implementation

Note :

Language :

انگليسي

Link To Document :