FPGA Implementation of Mean – Max Membership based Defuzzifier Unit

The output of fuzzification process, a fuzzy data, is unsuitable for real time applications and needs to be converted into a crisp value. The process of defuzzification is very important and has a significant impact on the overall performance of a fuzzy inference system. This paper proposes a VLSI architecture of a mean max membership (MMM) defuzzification method. The MMM of defuzzification is simple and is being generally used in comparison to more complex centre of gravity defuzzification method. The proposed architecture is modeled in very high speed hardware description language (VHDL) and implemented in Vertex-4 field programmable gate array (FPGA). The functional analysis has revealed that the proposed architecture is implementing MMM based defuzzifier accurately.