A Low Power Switchable Dual-Band Low-Noise Amplifier(LNA) for WLAN Applications

A Low Power Switchable Dual-Band Low-Noise Amplifier(LNA) for WLAN Applications

In this paper, design of a dual-band low-noise amplifier (LNA) is presented. The proposed dual-band LNA is designed using 0.18 μm CMOS technology for wireless area network (WLAN) applications. By switching the input inductance and output capacitance, the narrow-band gain and impedance matching are achieved at the 2.4 GHz and 5.2 GHz frequency bands, which reduces power consumption compared to the other structures. The proposed dual-band LNA has been simulated in the RF-TSMC 0.18 μm CMOS technology by Advanced Design System (ADS). The amplifier works at 0.9 V supply voltage with 3.2 mW power consumption. At 2.4-GHz, simulation results exhibit a noise figure of 1.5 dB, a power gain (S21) of 12.7 dB and an input return loss (S11) of -12.4 dB. In addition, the proposed LNA features a noise figure of 2.8 dB, a power gain (S21) of 16 dB and an input return loss (S11) of -16.6 dB at 5.2 GHz.

In this paper, design of a dual-band low-noise amplifier (LNA) is presented. The proposed dual-band LNA is designed using 0.18 μm CMOS technology for wireless area network (WLAN) applications. By switching the input inductance and output capacitance, the narrow-band gain and impedance matching are achieved at the 2.4 GHz and 5.2 GHz frequency bands, which reduces power consumption compared to the other structures. The proposed dual-band LNA has been simulated in the RF-TSMC 0.18 μm CMOS technology by Advanced Design System (ADS). The amplifier works at 0.9 V supply voltage with 3.2 mW power consumption. At 2.4-GHz, simulation results exhibit a noise figure of 1.5 dB, a power gain (S21) of 12.7 dB and an input return loss (S11) of -12.4 dB. In addition, the proposed LNA features a noise figure of 2.8 dB, a power gain (S21) of 16 dB and an input return loss (S11) of -16.6 dB at 5.2 GHz.