شماره ركورد كنفرانس :
3536
عنوان مقاله :
High Throughput Low Power CCMP Architecture for Very High Speed Wireless LANs
Author/Authors :
Alireza Hoseini Department of Electrical & Computer Engineering University of Tehran Tehran, Iran , Behnam Khodabandeloo Department of Electrical & Computer Engineering University of Tehran Tehran, Iran , Mahdi Jelodari Mamaghani Department of Electrical & Computer Engineering University of Tehran Tehran, Iran , Peyman Teymoori Department of Electrical & Computer Engineering University of Tehran Tehran, Iran , Nasser Yazdani Department of Electrical & Computer Engineering University of Tehran Tehran, Iran
كليدواژه :
IEEE 802.11 , Wireless Security Hardware Architecture , High Speed Wireless LANs , (Counter Mode with CBC-MAC Protocol (CCMP
سال انتشار :
دي 1394
عنوان كنفرانس :
پانزدهمين همايش بين المللي معماري كامپيوتر و سيستم هاي ديجيتال
زبان مدرك :
لاتين
چكيده لاتين :
Considering the pervasion of wireless portable devices and growing trends in the use of multimedia applications, access to a high speed and, especially, a high throughput wireless channel are of significant importance. In addition to security concerns in wireless devices, deficiency in throughput and also increase in power consumption are introduced to the system by applying security. Therefore, designing a secure, high-speed wireless device with low power consumption would be a suitable response to worldwide demands. In this paper, we propose a solution to reduce encryption overhead and we almost eliminate it. Furthermore, a customized hardware architecture for Counter Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) is proposed. This protocol is the fundamental security architecture of IEEE 802.11i standard. To improve throughput and reduce overhead, encryption is accomplished in the spare time intervals, such as DCF Inter-Frame Spaces (DIFS) used in IEEE 802.11i standard. In order to overcome the restrictions in dealing with these time intervals, a multi-core structure is proposed. Moreover, to reduce power consumption, a particular scheduler is implemented for processing cores. In the proposed architecture, we achieve up to 2Gbps throughput in the single core mode for MPDU (MAC Protocol Data Unit) and A-MSDU (Aggregated MAC Service Data Unit) input frames, and 17Gbps throughput in multi core mode for A-MPDU (Aggregated MPDU) input frames.
كشور :
ايران
تعداد صفحه 2 :
7
از صفحه :
1
تا صفحه :
7
لينک به اين مدرک :
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