16-bit Floating Point Math Unit for DSP Applications

Hardware support for floating point data manipulations has become mandatory for modern microprocessors and microcontrollers running multimedia applications. This paper presents 16-bit floating point coprocessor on reconfigurable hardware. Idea behind this work is using reconfigurable hardware along with 16-bit microprocessor (MPU) or microcontroller (MCU) units for faster calculations of floating point data. MPUs and MCUs supporting floating point arithmetic have limited number of multiply and accumulate (MAC) units (e.g., DSP C5520 has only two). Reconfigurable hardware makes the simultaneous calculations possible and augments the performance. Presented scheme is conversion of 16- bit signed fixed point number to 16-bit signed floating point representation, floating point representation to fixed point value, floating point multiplication and floating point addition. Algorithms for division is proposed. Data conversion and math operations are carried out in single clock cycle. Data conversion is asynchronous and multiplication and addition are partially asynchronous. Latency of proposed division algorithm depends on value of dividend. Latency of square root algorithm depends on the latency of division algorithm. Floating point format used is different than IEEE 754 half precision floating point format. However, standard format can be used by little change in the VHDL code. Reconfigurable hardware used here is SPARTAN III Field Programmable Gate Array (FPGA) product of Xlinx Inc. Xilinx ISE is used for synthesis of VHDL code and ModelSim 6.1 for simulation.