شماره ركورد كنفرانس :
3536
عنوان مقاله :
Reducing of Soft Error Effects on a MIPS-based Dual-Core Processor
Author/Authors :
Moslem Didehban Department of Computer Engineering and Information - Technology Amirkabir University of Technology Tehran, Iran , Saman Khoshbakht Department of Computer Engineering and Information - Technology Amirkabir University of Technology Tehran, Iran , Department of Computer Engineering and Information - Technology Amirkabir University of Technology Tehran, Iran , Hamid R Zarandi Department of Computer Engineering and Information - Technology Amirkabir University of Technology Tehran, Iran , Saadat Pourmozaffari Department of Computer Engineering and Information - Technology Amirkabir University of Technology Tehran, Iran
كليدواژه :
Dual-Core Processor , Soft Error Effects , MIPS
عنوان كنفرانس :
پانزدهمين همايش بين المللي معماري كامپيوتر و سيستم هاي ديجيتال
چكيده لاتين :
In this paper, a simulation-based fault injection
analysis of a MIPS-based dual-core processor is presented,
an approach is proposed to improve the reliability of most
vulnerable parts of the processor components and then the
improvement is evaluated. In the first series of experiments,
a total of 9100 transient faults were injected in 114 different
fault sites of the processor. These experiments demonstrate
that the Message Passing Interface, the Arbiter and the
Program Counters are the most vulnerable parts of the
processor. Thus, these parts were selected as targets for the
improvement. The fault tolerance method used for
improving the Arbiter is based on using the Triple Modular
Redundancy. As for the Message Passing Interface and the
Program Counters the single bit error correction Hamming
code is used. The experimental results show 11.8%
improvement in error recovery and 15.1% reduction of
failure rate at the cost of 1.01% area overhead.
