Improved Performance and Power Consumption of Three-dimensional FPGAs using Carbon Nanotube Interconnects

Three dimensional stacking and some new materials such as Carbon Nanotube are two efficient techniques to alleviate the interconnect problems. In this paper, utilizing the Carbon Nanotube interconnects in three-dimensional FPGAs is explored and a CNT/Metal hybrid routing architecture corresponding with a CNT-based routing algorithm is proposed. In the presented architecture, Through-silicon Vias and enough-long 2D wire segments are realized by CNT and remained wires are implemented by metal. Our experimental results show that critical delay and power consumption are improved by the proposed approach by about 30% and 21% on average for attempted benchmarks.