Reliability Improvement of Digital Circuits in the Presence of Process and Runtime Variations

Aging effects which degrades the digital circuit performance in the runtime, interacts with device parameter variation after fabrication leading to extreme reduction in circuit lifetime reliability. In this paper, a statistical circuit optimization method is proposed to ensure lifetime reliability of the manufactured chip in the presence of process variation and aging effects. The proposed method uses a variation-aware gate-level statistical aging degradation model to characterize circuit lifetime reliability and then, it identifies a set of statistically critical gates to estimate the worst delay degradations on these gates. Dual threshold voltage assignment technique is applied to the identified critical gates to enable the manufactured chip to satisfy lifetime reliability constraint in term of low performance overhead. Experimental results on ISCAS’85 benchmark circuits show that the proposed method increase the circuit reliability up to 14% imposing less than 10% performance overhead.