شماره ركورد كنفرانس :
5060
عنوان مقاله :
An Asymmetric Multi-Level Inverter Structure with Increased Steps per Devices
Author/Authors :
Fatemeh، Esmaeili Power Electronics Research Lab. (PERL) Faculty of Electrical Engineering - Sahand University of Technology، Tabriz, Iran , Kazem ، Varesi Power Electronics Research Lab. (PERL) Faculty of Electrical Engineering - Sahand University of Technology، Tabriz, Iran
كليدواژه :
number of steps/devices , capacitor based multi-level inverter , blocking voltage
عنوان كنفرانس :
11th Power Electronics, Drive Systems, and Technologies Conference (PEDSTC)
چكيده فارسي :
فاقد چكيده فارسي
چكيده لاتين :
This paper suggests an improved basic singlephase
35-level inverter unit that consists of 4 DC power supplies,
4 capacitors, 10 switch/diodes and 10 gate driver circuits. The
basic unit employs two DC links constructed by two cascaded
capacitors in parallel with VL and VR DC sources. The use of
capacitors not only has led to increased levels, but also has
reduced the DC sources and converter cost. The voltage
balancing of capacitors is done naturally which eases the control
of proposed topology. Since, the proposed structure is based on
developed H-bridge, it can produce positive, zero and negative
voltage steps. Also, the suggested topology has suitable
performance for resistive (R) or resistive-inductive (R-L) load
types. Based on comparison results, the suggested structure has
more steps per devices than similar configurations. The credits
of suggested topology have been certified by comparisons and
simulations in PSCAD/EMTDC software.
