DocumentCode :
1000287
Title :
A New Economical Implementation for Scannable Flip-Flops in MOS
Author :
Bhavsar, Dilip K.
Author_Institution :
Digital Equipment Corporation
Volume :
3
Issue :
3
fYear :
1986
fDate :
6/1/1986 12:00:00 AM
Firstpage :
52
Lastpage :
56
Abstract :
A New implementation for scannable flip-flops in MOS is economical for use in systems that use single latch design. The ¿System Latch-Scannable Flop¿ (SL-SF) requires two additional transfer gates, two test clocks, and possibly a test mode signal. Hardware pernalties paid in SL-SF can be the least among other implementations with equivalent test functionality. This article discusses SL-SF only in the context of its scan-path implementation; its applicability to linear feedback shift-register-based self-test should be obvious.
Keywords :
Built-in self-test; Circuit testing; Clocks; Design for testability; Flip-flops; Hardware; Latches; Master-slave; Multiplexing; System testing;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.1986.294994
Filename :
4069795
Link To Document :
بازگشت