Title :
A New Economical Implementation for Scannable Flip-Flops in MOS
Author :
Bhavsar, Dilip K.
Author_Institution :
Digital Equipment Corporation
fDate :
6/1/1986 12:00:00 AM
Abstract :
A New implementation for scannable flip-flops in MOS is economical for use in systems that use single latch design. The ¿System Latch-Scannable Flop¿ (SL-SF) requires two additional transfer gates, two test clocks, and possibly a test mode signal. Hardware pernalties paid in SL-SF can be the least among other implementations with equivalent test functionality. This article discusses SL-SF only in the context of its scan-path implementation; its applicability to linear feedback shift-register-based self-test should be obvious.
Keywords :
Built-in self-test; Circuit testing; Clocks; Design for testability; Flip-flops; Hardware; Latches; Master-slave; Multiplexing; System testing;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.1986.294994