DocumentCode
1000754
Title
Half-V CC sheath-plate capacitor DRAM cell with self-aligned buried plate wiring
Author
Kaga, Toru ; Kawamoto, Yoshifumi ; Kure, Tokuo ; Nakagome, Yoshinobu ; Aoki, Masakazu ; Sunami, Hideo ; Makino, Tohachi ; Ohki, Nagatoshi ; Itoh, Kiyoo
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
35
Issue
8
fYear
1988
fDate
8/1/1988 12:00:00 AM
Firstpage
1257
Lastpage
1263
Abstract
A trench-capacitor DRAM cell called a half-V CC sheath-plate capacitor (HSPC) cell has been developed using 0.6-μm-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 μm2 and excellent immunity (critical charge Q c<35 fC) against alpha-particle injection. These advantages are achieved using a half-V CC sheath-plate structure, a 5.5-nm SiO2-equivalent Si 3N4-SiO2 composite film, and three self-alignment technologies involving buried plate wiring, a sidewall contact and a pad for the bit-line contact. The device performance is evaluated using an experimental 2-kb array
Keywords
CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 16 Mbit; 2 kbit; 51 fF; 600 nm; CMOS; HSPC cell; Si3N4-SiO2 composite film; alpha particle immunity; bit-line contact; cell area; device performance; experimental 2-kb array; half-VCC sheath-plate capacitor; self-aligned buried plate wiring; self-alignment technologies; sheath-plate capacitor DRAM cell; sidewall contact; storage capacitance; submicron process technology; trench-capacitor DRAM cell; CMOS process; Capacitance; Impurities; Insulation; MOS capacitors; MOSFETs; Random access memory; Substrates; Voltage; Wiring;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.2545
Filename
2545
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