A method for characterizing a microprocessor´s vulnerability to SEU

Author

Elder, J.H. ; Osborn, J. ; Kolasinski, W.A. ; Koga, R.

Author_Institution

Aerospace Corp., Los Angeles, CA, USA

Volume

35

Issue

6

fYear

1988

fDate

12/1/1988 12:00:00 AM

Firstpage

1678

Lastpage

1681

Abstract

A system has been developed that tests microprocessors for single-event upset (SEU) at the specified clock speed and without adding wait or hold states. This system compiles a detailed record of SEU-induced errors and has been used to test the Sandia SA3000 microprocessor and prototypes of its commercial equivalent, the Harris H80C85 at the Lawrence Berkeley Laboratory 88-inch cyclotron facility. Using appropriate test programs and analyzing the resulting upset data, the authors have established the SEU cross section of the major functional elements of the hardened processors. With these cross sections and the estimated duty factors of a `typical´ program, they computed the expected upset rate in a parallel, normally incident, beam as a function of linear energy transfer and measured the rate in several cyclotron beams. Good agreement between the measured and calculated rates was obtained

Keywords

ion beam effects; microprocessor chips; radiation hardening (electronics); Harris H80C85; Sandia SA3000; clock speed; cyclotron beams; duty factors; hardened processors; linear energy transfer; microprocessors; single-event upset; upset rate; vulnerability; Aerospace testing; Clocks; Cyclotrons; Laboratories; Microprocessors; Prototypes; Registers; Single event upset; Software testing; System testing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.25521

Filename

25521