DocumentCode
1002181
Title
Designing the Micro/370
Author
Chao, H.H. ; Ong, S. ; Tsai, M. ; Shih, F.W. ; Lewis, K.W. ; Tang, J.Y.F. ; Trempel, C.A. ; Yu, H.N. ; McCormick, P.E. ; Davis, C.V., Jr. ; Diamond, A.L. ; Medve, T.J. ; Hou, J.C.L.
Author_Institution
IBM T. J. Watson Research Center
Volume
4
Issue
3
fYear
1987
fDate
6/1/1987 12:00:00 AM
Firstpage
32
Lastpage
40
Abstract
The first System/370 microprocessor, the Micro/370 is a 32-bit processor that implements 102 System/370 instructions and supports the emulation of the rest of the instructions. The chip is 10 mmx 10 mm with 200,000 transistor sites, fabricated with a 2-micron polysilicon gate NMOS technology with two levels of aluminum. It is designed for 10 MHz clock at worst case and has been operated at 18 MHz with 3W power dissipation. Design tasks included maximizing the noise margin, minimizing noise, and being able to complete design changes in a short time. A mixed custom and standard-cell design approach was used in a hierarchical design and verification methodology.
Keywords
Circuit noise; Circuit testing; Clocks; Design methodology; Design optimization; Emulation; Frequency; MOS devices; Microarchitecture; Microprocessors;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.1987.295163
Filename
4069989
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