Second substrate current peak and its relationship to gate-voltage dependent series resistance in submicrometre nMOS LDD transistors

The occurrence of the second substrate current hump (SSCH) has been thoroughly investigated and it is well known that the lateral electric field at the source side (E_s) is responsible for the appearance of the SSCH in submicrometre nMOS LDD transistors. However the fall off of the SSCH after reaching a maximum value, the so called second substrate current peak (SSCP), is not well understood and explained. Here an improved model of the lateral electric field at the source side, which explains the SSCP in terms of the dependence of the source series resistance R_is on the gate-source voltage, is introduced.