Stray-free switched-capacitor unit-delay circuit

A two-phase stray-insensitive switched-capacitor unit-delay circuit utilising only one operational amplifier is presented. The implementation of sampled analogue filters based on digital-filter architectures using this circuit as a building block is demonstrated. A final application of the unit delay, a switched-capacitor interpolator which effectively doubles the sampling frequency of the output of an analogue discrete-time system, is shown.