High-Pressure Deuterium Annealing Effect on Nanoscale Strained CMOS Devices

Author

Cho, Sung-Man ; Lee, Jeong-Hyun ; Chang, Man ; Jo, Min-Seok ; Hwang, Hyun-Sang ; Lee, Jong-Kon ; Hwang, Sung-Bo ; Lee, Jong-Ho

Author_Institution

Kyungpook Nat. Univ., Daegu

Volume

8

Issue

1

fYear

2008

fDate

3/1/2008 12:00:00 AM

Firstpage

153

Lastpage

159

Abstract

High-pressure deuterium annealing was applied to nanoscale strained CMOS devices, and its effect was characterized in terms of charge pumping method, hot-carrier-induced stress, negative bias temperature instability stress, and 1/f noise for the first time. For the NMOS, the characteristics of both control and tensile-stressed NMOS devices were improved by annealing; in particular, tensile-stressed NMOS devices had more improved characteristics than the characteristics of control devices. However, for the PMOS, compressive-stressed PMOS devices particularly had more degraded characteristics compared with the characteristics of control PMOS devices.

Keywords

CMOS integrated circuits; hot carriers; charge pumping method; high-pressure deuterium annealing effect; hot-carrier-induced stress; nanoscale strained CMOS devices; negative bias temperature instability stress; tensile-stressed NMOS devices; 1/f Noise; $hbox{1}/f$ noise; CMOS; Charge pumping; Deuterium Annealing; High pressure; Hot carrier stress; Nano-scale; Negative Bias Temperature Instability stress; deuterium (D) annealing; high pressure; hot carrier stress; nanoscale; negative bias temperature instability (NBTI) stress; strained;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2007.914014

Filename

4399958