DocumentCode :
1003812
Title :
Hardware-software design and validation framework for wireless LAN modems
Author :
Drosos, C. ; Bisdounis, L. ; Metafas, D. ; Blionas, S. ; Tatsaki, A. ; Papadopoulos, G.
Author_Institution :
INTRACOM S.A, Athens, Greece
Volume :
151
Issue :
3
fYear :
2004
fDate :
5/19/2004 12:00:00 AM
Firstpage :
173
Lastpage :
182
Abstract :
The implementation and validation of a 5-GHz wireless LAN modem based on the HIPERLAN/2 standard is presented. In modern wireless communication systems, there is a demand for higher flexibility and more computational efficiency. Therefore the emphasis of this work is on the hardware-software structure of the developed modem and its processes, in order to offer a good balance of these requirements. In order to efficiently design and validate the behaviour of the modem, a behavioural model was developed in UML (Unified Modelling Language) as a part of the overall HIPERLAN/2 system´s model. The processes of the modem were implemented in an instruction-set processor and custom hardware, combining the advantages of both software and hardware implementations. The communication between the software and hardware parts of the modem is achieved through a specialised programmable interface unit. The UML-based model of the actual HIPERLAN/2 system is used in order to validate the modem´s behaviour, using scenarios from in-field usage (such as transfer of data using FTP or HTTP). Furthermore, the validation of the algorithms implemented within the modem was based on this system model, and performed through the use of a custom-validation framework. This framework produces patterns for the validation of the modem´s algorithms, at three different development phases (algorithmic, HDL, FPGA-based prototyping), derived from the simulation of the system model in a consistent and automatic way. Implementation figures and co-simulation results for the developed wireless LAN modem are also given.
Keywords :
automatic test pattern generation; combinational circuits; fault simulation; logic testing; ISCAS-89 benchmark circuits; combinational logic; fault subset identification; fault-dominance relations; full-scan circuits; maximally dominating fault set; maximally dominating faults; n-detection test sets; n-detection tests; structural analysis; test generation;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:20040496
Filename :
1304178
Link To Document :
بازگشت