Design and fabrication of a 4Mbit bubble memory chip with 4 µm period permalloy propagation tracks

A 4 Mbit bubble memory chip with a 4 μm period "Wide Gap" pattern was designed and fabricated. Results obtained in the optimization of the 4 μm period "Wide Gap" pattern previously reported [1], led us to employ a dual-spacing layer structure. In addition to these technologies, a 4 Mbit chip was designed with relaxed function designs [2] and folded minor loop organization. The submicron pattern gaps in the 4 μm period tracks were delineated using a 10 to 1 projection aligner. A Cr2O3antireflection layer on the permalloy film was employed to improve a usable resolution of the aligner. The optimized thickness of the Cr2O3layer almost entirely eliminated the reflected light at the bottom of the resist making it possible to delineate 0.85 μm gaps in production. The reproducibility of the 4 Mbit chip was improved by varying the spacing for the 4 μm period tracks and the overall bias margin of 15 Oe was obtained with fully-loaded pages.