A frequency compensation scheme for LDO voltage regulators

Author

Chava, Chaitanya K. ; Silva-Martínez, José

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

51

Issue

6

fYear

2004

fDate

6/1/2004 12:00:00 AM

Firstpage

1041

Lastpage

1050

Abstract

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-μm CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time.

Keywords

CMOS integrated circuits; circuit stability; compensation; voltage regulators; 0.5 micron; CMOS technology; ESR capacitive loads; LDO stability; LDO voltage regulators; equivalent series resistance; frequency compensation; ground current; linear regulators; load regulation; multilayer ceramic capacitors; power management; stable low dropout regulator; CMOS technology; Capacitors; Frequency; Low voltage; Noise robustness; Nonhomogeneous media; Paramagnetic resonance; Regulators; Stability; Topology; Frequency compensation; LDO; LDO stability; linear regulators; low dropout; power management; regulator;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2004.829239

Filename

1304961