DocumentCode :
1012473
Title :
Design trade-offs for user-level I/O architectures
Author :
Schaelicke, Lambert ; Davis, Alan L.
Author_Institution :
Intel Corp., Ft. Collins, CO
Volume :
55
Issue :
8
fYear :
2006
Firstpage :
962
Lastpage :
973
Abstract :
To address the growing I/O bottleneck, next-generation distributed I/O architectures employ scalable point-to-point interconnects and minimize operating system overhead by providing user-level access to the I/O subsystem. Reduced I/O overhead allows I/O intensive applications to efficiently employ latency hiding techniques for improved throughput. This paper presents the design of a novel scalable user-level I/O architecture and evaluates the impact of various architectural mechanisms in terms of overall performance improvement. Results demonstrate that eliminating data movement across protection domains is the dominant contributor to improved scalability. Eliminating system call and interrupt overhead only has a small additional benefit that may not justify the additional hardware support required. While this evaluation is based on one specific design, the conclusions can be generalized to other user-level I/O architectures
Keywords :
input-output programs; memory architecture; performance evaluation; storage management; data movement; hardware support; input/output device; interrupt overhead; latency hiding technique; next-generation distributed I/O architecture; operating system overhead; point-to-point interconnect; reduced I/O overhead; system call overhead; user-level I/O architecture design; user-level access; Analytical models; Computer architecture; Delay; Hardware; Operating systems; Performance analysis; Protection; Random access memory; Scalability; Throughput; Architecture; input/output devices; performance analysis; simulation.; user-level;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2006.122
Filename :
1650194
Link To Document :
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