DocumentCode :
1014560
Title :
The ELSA wafer scale integration project
Author :
Ivey, Peter
Author_Institution :
Dept. of Electron. & Electr. Eng., Sheffield Univ., UK
Volume :
16
Issue :
7
fYear :
1993
fDate :
11/1/1993 12:00:00 AM
Firstpage :
626
Lastpage :
636
Abstract :
Outlines some of the technology, successful and unsuccessful, of part of a large European project in wafer scale integration (WSI). The work described is an attempt to build a 64 by 64 array processor on a 4-in wafer. Such a processor would have a computing power in excess of 10 billion operations per second. A test chip and a demonstration system, which achieves such a processing power, is also described
Keywords :
VLSI; microprocessor chips; parallel architectures; ELSA wafer scale integration project; array processor; computing power; demonstration system; parallel processing; test chip; Application software; Computer architecture; Hardware; Helium; Packaging; Prototypes; Silicon; Software tools; System testing; Wafer scale integration;
fLanguage :
English
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
0148-6411
Type :
jour
DOI :
10.1109/33.257872
Filename :
257872
Link To Document :
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